1. Field of the Invention
The present invention relates to a dry etching method, and more specifically, to a dry etching method of a silicon substrate for manufacturing semiconductor devices.
2. Description of the Related Art
Recently in the field of semiconductor devices, along with the advancement of low power consumption, improved operation speed and higher integration, one of the problems to be solved is the isolation of semiconductor elements and the securing of memory/cell capacity area. One of the methods for solving the problem is a process for forming trenches on a silicon substrate, wherein element isolation is realized by a method called a shallow trench isolation method (hereinafter referred to as STI method).
The STI method is composed of a process for forming trenches on a semiconductor substrate, and a process for embedding insulating films into the trenches and planarizing the same. Thus, in order to perform element isolation via the STI method, it is necessary to first form trenches on the semiconductor substrate.
Usually according to a photolithography method and etching method, a resist pattern is formed, and the patterned resist is used as a mask to perform etching. However, in order to etch a hard layer such as a substrate on which the trenches are formed (what is meant by “hard” is that the material has a relatively small etching rate with respect to common materials to be etched), the resist itself is weak, and therefore, it cannot be used alone as mask. Therefore, an etching mask so-called a hard mask, such as a nitride film or an oxide film, is used.
The hard mask must also be patterned through a photolithography method and etching method. With the resist remaining on the hared mask, or after removing the resist, the hard mask is used to form trenches on the semiconductor substrate. After forming trenches, an insulating film such as a silicon oxide film is embedded in the trenches via a CVD method or the like, and therefore, a process of planarizing the surface of the substrate is performed via a chemical mechanical polishing (CMP) method, by which the STI method is realized.
According to the STI method performed in the above manner, when etching a wafer having a patterned mask 21 disposed on a silicon substrate 20 as illustrated in FIG. 4A, the portion where the dimension width (or area) exposing the silicon as substrate material is narrow (portion where the mask pattern is dense) has a lower etching rate than a wider portion (portion where the mask pattern is isolated), which is a so-called micro loading effect. As a result, as shown in FIG. 4B, the present micro loading effect causes the amount of etching of the portion where the pattern is dense to be smaller than the amount of etching of the portion where the pattern is isolated, so that it is difficult to form trenches with a desired depth.
The mechanism of the micro loading effect is considered to be caused mainly by the difference in the amount of radicals being incident per unit time on the portion where the mask pattern is isolated and on the portion where the mask pattern is dense (since radicals are capable of isotropic free motion). That is, in the portion where the mask pattern is dense, the incidence of radicals is blocked by the surrounding mask, so that the etching rate is extremely lowered compared to where the mask pattern is isolated.
One method for solving the problem is disclosed in Japanese patent application laid-open publication No. 2001-053138 (patent document 1). The disclosed art relates to implanting inactive ions into a portion where silicon is exposed prior to etching the silicon substrate, turning a portion thereof into amorphous and mainly etching said portion. Since according to the method the ions realize anisotropic incidence, the mask pattern has very little isolated-dense dependency during etching (here, what is meant by the mask pattern being isolated or dense is that abstract concepts of the property that the mask pattern is “isolated” or that the mask pattern is “dense” are extracted). Therefore, only the portions that must be etched intrinsically is turned into amorphous and removed.
Another art is disclosed in published Japanese translations of PCT international publication No. 2004-507086 (patent document 2), according to which a resist mask is removed prior to etching the silicon substrate, and the aspect ratio between patterns is reduced, so that anisotropic etching is performed via ion assisted etching.